1. Field of the Invention
The present invention relates to a metal pattern and a method of forming the same, and more particularly to a metal contact pattern and a method of forming the metal contact pattern for use in a semiconductor apparatus, such as a mask programmable read only memory, a photoelectrical conversion apparatus or a signal processing apparatus, a semiconductor apparatus which includes an electrostatic capacity device, a semiconductor integrated circuit including an LDD transistor and a Schottky-diode or an image reading or recording semiconductor device.
2. Related Background Art
The conventional technology has experienced the following problems at the time of forming a pattern on an electrode or the like of the foregoing devices.
(1) Selective Formation of Contact of Mask ROM
A mask ROM is a semiconductor memory for exclusively use to write data with a mask for photolithography for use in a process for manufacturing a semiconductor. The mask ROM is widely used to serve as a fixed memory of a computer, a data memory of a kanji generator or a voice synthesizer or program software of a TV game. FIG. 1 is a circuit diagram of the mask ROM having MOS transistors which are disposed to form a matrix and on which data is written. Since a variety of methods of writing data on the mask ROM are available, corresponding manufacturing methods are employed. Data is written by a method in which the threshold voltage of the gate is varied or a method in which data is written depending upon whether or not the contact is present on the drain region of the transistor. The threshold voltage of the gate is varied by a method in which the thickness of an oxide film of the gate is changed, a method in which channel dope ions are selectively injected after the gate oxide film has been formed, a method in which channel dope ions are further selectively injected through a polysilicon electrode with high energy after the polysilicon gate electrode has been formed or a method in which channel dope ions are selectively injected through an aluminum circuit or a passivation film with large energy of 1 MeV or larger after the aluminum circuit or the passivation film has been formed. The foregoing methods will now be described. The method in which the thickness of the gate oxide film is changed and a method in which the channel dope ions are selectively injected by a photolithographic mask after the gate oxide film has been formed are omitted from description because they encounter a problem that a too long manufacturing process must be performed after data has been written.
FIGS. 2A to 2C illustrate the process for manufacturing the mask ROM by the conventional method, in which the injection of the channel dope ions is performed selectively through the polysilicon electrode with high energy after the polysilicon gate electrode has been performed to write data. FIG. 2A illustrates the cross section of MOS transistors formed by a known technology. Field oxide films 2 are formed on a P-type Si substrate 1, and the MOS transistor devices are separated from each other. Gate electrodes 4 made of polysilicon are formed on gate oxide films 3, and channel regions 5 are formed under the gate oxide films 3. Further, source regions 6 and drain regions 7 are formed so that an inter-layer insulating film 8 in the form of a non-dope silicate glass (NSG)/BPSG structure is formed by CVD. It should be noted that proper channel doping is performed in the channel regions 5 by ion injection. That is, the state where the MOS transistor is turned off is maintained even if voltage corresponding to negative logic "0" is applied to the gate. If voltage corresponding to positive logic "1" is applied to it, the MOS transistor is turned on. FIG. 2B illustrates a manufacturing process corresponding to writing of data. After a photo-resist 20 has been applied, a mask on which data is written is used to pattern the photo-resist 20. Then, B-ions 21 are injected under conditions that energy is about 200 KeV to about 400 KeV and the amount of dose is about 1.times.5.times.10.sup.13 cm.sup.-12 if the minimum size is determined by a 1.2 .mu.m rule although the foregoing conditions are varied depending upon the degree of integration of the mask ROM. The thickness of the photo-resist is determined depending upon the energy. After channel dope ions for writing data have been injected, the photo-resist 20 is removed to reflow the inter-layer insulating film. The reason why the reflow is performed is that the inter-layer insulating film must be flattened and the channel-doped ions B must be electrically activated. AMOS transistor positioned in the right portion of FIG. 2B has the channel region 5 in which ions B are doped so that the threshold voltage is sufficiently higher than the voltage corresponding to the positive logic "1". Therefore, even if the voltage corresponding to the positive logic "1" is applied to the gate, the state where the right MOS transistor is turned off is maintained. FIG. 2C illustrates the final cross sectional structure. Contact holes 9 are formed in the source region 6, the gate oxide film 3 on the drain region 7 and the inter-layer insulating film 8, and aluminum lines 18 are formed so that a passivation film 19 made of SiN is formed.
FIGS. 3A and 3B illustrate a process for manufacturing a mask ROM by the conventional method. The foregoing method is a method in which aluminum lines or a passivation film is formed, and then the channel dope ion injection is selectively performed through the aluminum lines or the passivation film with large energy of 1 MeV or larger so that data is written. FIG. 3A illustrates the cross section of a state where MOS transistors are formed by the known method. A field oxide film 2 is formed on the P-type Si substrate 1 and the MOS transistor devices are separated from one another. Channel regions 5 are formed under gate oxide films 3. Further, source regions 6 and drain regions 7 are formed so that an inter-layer insulating films 8 in the form of the (NSG)/BPSG structure are formed by CVD. Contact holes 9 are formed through the source regions 6, the gate oxide films 3 on the drain regions 7 and the interlayer insulating films 8 so that aluminum lines 18 are formed. Further, a passivation film 20 made of SiN is formed. In this example, the aluminum lines 18 are not present on the gate electrodes 4. Proper channel doping is performed in the channel regions 5 by ion injection. That is, even if voltage corresponding to negative logic "0" is applied to the gate, the state where the MOS transistor is turned off is maintained. However, if voltage corresponding to positive logic "1" is applied to the gate, the MOS transistor is turned on.
FIG. 3B illustrates a manufacturing process corresponding to writing of data. After a photo-resist 20 has been applied, a mask on which data is written is used to pattern the photo-resist 20. Then, B-ions 21 are injected under conditions which vary depending upon whether or not the aluminum line 18 is present on the gate electrode 4 of the mask ROM or whether or not the channel dope ion injection for writing data is performed through the passivation film 19. Energy of 1 MeV or larger is needed, and the amount of the dose is about 1 to 10.times.10.sup.13 cm.sup.-2. After channel dope ions for writing data have been injected, the photoresist 20 is removed. Then, heat treatment is performed in order to electrically activate channel-doped ions B. Since the aluminum lines 15 have been formed, the heat treatment is performed at 450.degree. C. or lower. The right MOS transistor shown in FIG. 3B has the channel region 5 in which ions B are doped so that the threshold voltage is sufficiently higher than the voltage corresponding to the positive logic "1". Therefore, even if the voltage corresponding to the positive logic "1" is applied to the gate, the state where the right MOS transistor is turned off is maintained. The foregoing second conventional example has no ensuing process.
FIGS. 4A to 4B illustrate a third conventional example of the process for manufacturing the mask ROMs, wherein data is written depending upon whether or not a contact is present on a drain region. FIG. 4A illustrates the cross section of a state where MOS transistors are formed by the known technology. A field oxide film 2 is formed on a P-type Si substrate, and the MOS transistor devices are separated from one another. Gate electrodes 4 made of polysilicon are formed on gate oxide films 3. Further, channel regions 5 are formed under the gate oxide films 3. In addition, source regions 6 and drain regions 7 are formed so that an inter-layer insulating film 8 in the form of an NSG/BPSG structure is formed by CVD. Proper channel doping is performed in the channel regions 5 by ion injection. That is, even if voltage corresponding to negative logic "0" is applied to the gate, the state where the MOS transistor is turned off is maintained. If voltage corresponding to positive logic "1" is applied to the gate, the MOS transistor is turned on.
FIGS. 4B and 4C illustrate a manufacturing process which corresponds to writing of data. After a photo-resist 20 has been applied, a mask, on which data has been written, is used to pattern the photoresist 20. Then, contact holes 9 are formed in the source regions 6, the gate oxide film 3 on the drain regions 7 and the inter-layer insulating film 8 before 1 aluminum lines 18 are formed. The right MOS transistor shown in FIG. 4C has no contact hole in the gate insulating film 3 on the drain region 6 and the inter-layer insulating film 8. Therefore, the right MOS transistor is not applied with power supply voltage VDD. Therefore, even if voltage corresponding to positive logic "1" is applied to the gate, the state where the MOS transistor is turned off is maintained. FIG. 4D illustrates a final cross section. Thus, a passivation film 19 made of SiN is formed.
Since data is written on the mask ROM in the manufacturing process, it has considerable custom characteristics. Therefore, the mask ROM must be delivered in a short period (TAT: time around time) from a moment of receipt of data from a customer to a moment of delivery as well as meeting requirements, such as high degree of integration, low electric power consumption and low cost and the like, generally required for a memory. If the data writing process is performed in the first half of the manufacturing process, an error of written data or that occurring in the mask manufacturing process causes the delivery data to be further delayed.
Although the first conventional example exhibits a relatively short TAT because data is written after the gate electrode has been formed, the TAT is longer than that realized by the second or the third conventional example. Even worse is, the fact that data writing can be performed by injecting ions with large energy of 200 to 400 KeV prevents use of a general ion injecting apparatus. Therefore, an exclusive large-energy ion injecting apparatus must be used and, accordingly, the cost to manufacture the mask ROM cannot be reduced.
Since the second conventional example is arranged to write data after the passivation film has been formed, it exhibits a considerably short TAT which takes one or two days in addition to days taken to manufacture the mask. However, the heat treatment can be performed only under a low temperature of 450.degree. C. or lower after the aluminum lines have been performed. Therefore, defects generated due to the injection of channel dope ions for writing data cannot be recovered completely. Further, only about 50% of channel-doped ions B can be electrically activated. If ions are injected with large energy in MeV levels, there arises a problem in that defects cannot completely be restored even if the heat treatment is performed at high temperature. Therefore, a problem of reliability arises. Further, if the aluminum line is present on the gate electrode, the channel dope ion injection causes aluminum atoms to be introduced into the gate channel region due to the knock-on phenomenon. What is worse, the cost to manufacture the mask ROM cannot be reduced as compared with the first conventional example because the price of the MeV-level high energy ion injecting apparatus is high and its manufacturing performance is unsatisfactory.
The third conventional example does not need a special manufacturing apparatus raising the cost to manufacture the mask ROM and exhibits a short TAT as compared with the first conventional example. However, the necessity that the contact region is formed for each memory cell raises a technical problem in that the chip area cannot be reduced.
With any one of the foregoing methods, many days are required to manufacture the mask on which data will be written. It leads to a fact that the mask must be manufactured again if there is a data error. Therefore, even if the TAT is short after the mask has been manufactured, the overall TAT cannot be shortened satisfactorily.
(2) Semiconductor Integrated Circuit Having Capacitor